In applications which are based on embedding a semiconductor chip in a polymer or plastic compound in such a way that the upper sides of semiconductor chip and plastic compound form an overall upper side, such as is provided, for example, in multi-chip module technology or MCM technology or in chip-in-polymer technology, starting from the active upper sides of the semiconductor chips with their contact areas, rewiring is needed in order to connect the contact areas of the semiconductor chips to external contact areas on the overall upper side for a predefined external contact pattern. To this end, the semiconductor chips in the panel made of a plastic compound are accommodated in component positions. The component positions of the panel are arranged in rows and columns, the edges of the semiconductor chips running parallel to the columns and rows of the panel.
The rewiring in each of the component positions of the panel is implemented by rewiring layers in the form of a sequence of metal and dielectric layers. The structuring of the individual layers is carried out by means of deposition processes, which are carried out over the entire area, and by photolithography processes, in which the deposits over the entire area are structured. These photolithography processes can be carried out simultaneously for a plurality of component positions on the overall upper side of the panel if extremely close tolerances of a few micrometers are maintained when aligning the semiconductor chips in the component positions. However, within the panel, the problem arises that the chips to be wired exhibit position inaccuracies because of the population tolerances during the production of the panel. Position inaccuracies of this type can lead to considerable failures in the yield occurring with the conventional exposure processes of photolithography.
Given an order of magnitude of the contact areas of 90 μm, a minimum accuracy for the alignment of the semiconductor chips within the rows and columns of the component positions of ±25 μm must be maintained. In the event of greater position deviations of the semiconductor chips in the component positions, contact areas which are no longer reached by rewiring can already occur. Compensating for position errors of semiconductor chips in the component positions of a panel is possible by using a laser writing method, in which a photoresist layer is exposed by a write laser. However, because of the high rewiring densities required on a panel and the size of the area to be exposed for each panel, this exposure by means of scanning with a laser write beam is a time-consuming method and disadvantageously associated with high process costs.
A further possible way of compensating for position errors which go beyond a minimum tolerance compensation would be the possibility of exposing each component position individually and providing all the component positions of the panel with rewiring sequentially one after another. In this case, a mask is realigned in each of the component positions of the panel, so that, although the position errors of the chip are compensated for for the rewiring, the position error is transferred to the arrangement of the external contact areas and therefore to the external contacts that are visible from outside. This method likewise results in a low throughput as a result of the sequential processing of the panel, as compared to the use of a single overall mask which manages with one exposure process.
A further disadvantage is that, as a result of the independent adjustment of each individual installation location, although the position errors of the semiconductor chips are compensated for, the individual alignment means that a uniform grid no longer results for the matrix and the pattern of the external contacts. The external contacts of the individual component positions are then no longer located parallel to the outer edges of the semiconductor components but exhibit an X/Y offset or a rotation with respect to one another. Such a nonuniform pattern of the external contact areas on account of the position errors of the semiconductor chips also leads to problems in applying the external contacts in the form of solder globules in a compliant manner, since both the printing processes and the deposition by electroplating, and the mechanical alignment of solder globules assume a defined and reproducible pattern dimension within the context of a uniform matrix.
Following separation, in this method of the individual compensation for the position errors, an electronic component is produced with housings which have a solder globule pattern with varying positions in relation to the housing edge. This can in turn lead to problems during testing and during the further processing or the use of the electronic components in a fabrication plant if the position errors become greater than those permitted by the JEDEC Standards.
For this and other reasons, there is a need for the present invention.